The present invention relates generally to integrated circuit testing, and more particularly to a method of monitoring enhanced status during scan testing.
As the gate density of integrated circuits (ICs) increases, semiconductors are being manufactured today that have a much higher ratio of gate count to external package pin count. The result is that the test coverage of the circuits can be limited unless some additional package pins are dedicated to testing and additional testability is designed into the ICs.
Structured testing techniques that require dedicated test pins include Design For Testability (DFT) approaches such as scan testing, Built-In Self-Test (BIST), and Random Access Scan. However, because the number of external pins is limited, dedicated test pins are provided at the cost of reduced functionality and reduced normal run-time accessibility of functional modules of the circuit that would otherwise be possible using those pins.
Additionally, traditional scan tests are used to check for stuck-at faults, transistor faults, bridging faults, open faults, delay faults, and other types of faults, but do not concurrently capture other global or specialized status information of the chip that may be relevant to those failures.
FIG. 1 is a simplified block diagram illustrating a conventional integrated circuit (IC) 100 that has been designed to support scan testing. The IC 100 includes a core logic block 110 with integrated Design For Test (DFT) circuitry, a clock source module 120, and a power source module 130.
The core logic block 110 receives inputs via the input data signal scan_din 140, which provide scan pattern inputs, and the clock signal scan_clk 150, which provides a clock for scanning scan test patterns into and out of the IC 100. The core logic block 110 outputs data via the output data signal scan_dout 160, as would be understood to one familiar with scan testing. Each of the above inputs, clocks, and outputs is associated with a pin on the IC package. Other inputs and outputs for functional operation of the core logic are not shown for purposes of clarity of this discussion.
The clock source module 120 includes an input clock signal test_clk 170 and generates a core logic clock signal clk 180 that connects to the core logic block 110. The clock source module 120 includes a crystal and PLL (phase locked loop) with divider (not shown) for generating the on-board clocks for the core logic block 110 to use during regular operation, and selector logic (not shown) for selectively allowing the core logic clock signal clk 180 to be driven directly by the input clock signal test_clk 170 under test conditions.
The power source module 130 is connected to power and ground connections (not shown) external to the IC 100 and generates the various voltages and currents used by the IC 100, specifically the core logic block 110, during operation and testing. The power source module 130 may also have bypass circuitry (not shown) for external provision of specific voltages to certain test points of the circuit during testing.
Note that the signals scan_din 140, scan_clk 150, scan_dout 160, and test_clk 170 require dedicated test pins that could otherwise be utilized in the IC 100 for direct functional I/O, power, and/or ground. In other words, the test inputs/outputs are using up valuable pins on the IC 100. Additionally, while the design of the IC 100 provides for monitoring typical scan test faults, it fails to provide a mechanism for monitoring other status information associated with the state of the IC 100 that may be relevant to the failures being detected via scan test or otherwise.